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[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 基于FPGA的rom程序（verilog）-rom procedure
Platform: | Size: 2048 | Author: 杨涛 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 基于verilog的双口和单口RAM的实现-Verilog dual port and single port RAM-based implementation
Platform: | Size: 137216 | Author: xinghe | Hits:

[VHDL-FPGA-Verilog] verilog-code

Description: 都是verilog代码：多路选择器代码，储存器代码，时钟分频器代码，串并转换电路代码，香农扩展运算代码，ram代码。-MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
Platform: | Size: 2439168 | Author: ponyma | Hits:

[VHDL-FPGA-Verilog] verilog--sram

Description: ram的fpga应用，用verilog语言实现，适用于cyclone 2系列-ram the fpga application verilog language applicable to cyclone 2
Platform: | Size: 96256 | Author: sunlin | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
Platform: | Size: 115712 | Author: an | Hits:

[VHDL-FPGA-Verilog] LPM_RAM

Description: verilog 参数可设置调用模块RAM-verilog parameter can be set to call the module RAM
Platform: | Size: 146432 | Author: water | Hits:

[DSP program] RAM-verilog

Description: 非常 好的资料，希望大家都能喜欢， 谢谢大家的支持-Very, very good information, I hope people will like it, thank you for your support
Platform: | Size: 59392 | Author: 程稻蕾 | Hits:

[Other] RAM

Description: 通过使用fpga，verilog语言来实现RAM的读写功能。-for ram reading and writing
Platform: | Size: 4600832 | Author: 言艳 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog 常用模块，包含设计模块和测试模块，如有ram, lifo等-verilog useful blocks
Platform: | Size: 1010688 | Author: 陆美希 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
Platform: | Size: 2048 | Author: 刘泽 | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用verilog实现了IP核的使用，例化了一个RAM，用来进行读写操作，另外还编写了斐波那契数列来进行测试。-Using verilog to achieve the use of IP core, the instantiation of a RAM, used to read and write operations, in addition to the preparation of the Fibonacci sequence for testing.
Platform: | Size: 3072 | Author: east | Hits:

[VHDL-FPGA-Verilog] fpga

Description: pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
Platform: | Size: 13411328 | Author: 峰语 | Hits:

[VHDL-FPGA-Verilog] pudn

Description: Encoders, decoders and RAM Model
Platform: | Size: 11264 | Author: sheldon01 | Hits:

[VHDL-FPGA-Verilog] 各种基础module打包下载全集

Description: 例如分频器，alu，ram的verilog实现(The implementation of divider, alu, ram etc. in verilog)
Platform: | Size: 7168 | Author: Harrypotterrrr | Hits:

[VHDL-FPGA-Verilog] ram rom verilog

Description: ram rom verilog hdl verilog
Platform: | Size: 5618 | Author: mamine2ia | Hits:

[VHDL-FPGA-Verilog] ARM_SOC

Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
Platform: | Size: 688128 | Author: ldz13180882132 | Hits:

[VHDL-FPGA-Verilog] 实验九 计算机核心（CPU+RAM）的设计与实现

Description: 计算机组成原理的CPU实验，基于quartus平台(CPU experiment of computer organization principle, based on quartus platform)
Platform: | Size: 3360768 | Author: 丁丫头 | Hits:

[VHDL-FPGA-Verilog] Memory Verilog

Description: ROM,RAM (dual port)- Verilog
Platform: | Size: 1585 | Author: gsrwork2017@gmail.com | Hits:
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